module display (
    input clk,
    input rst,
    input [31:0] data,
    output reg [7:0] seg,
    output reg [2:0] sel
);

  always @(posedge clk or negedge rst) begin
    if (!rst) begin
      sel <= 3'd0;
    end else begin
      sel <= sel + 3'd1;
    end
  end

  reg [4:0] num;

  always @(*) begin
    case (sel)
      3'b000:  num = {1'b0, data[31:28]};
      3'b001:  num = {1'b0, data[27:24]};
      3'b010:  num = {1'b0, data[23:20]};
      3'b011:  num = {1'b0, data[19:16]};
      3'b100:  num = {1'b1, data[15:12]};
      3'b101:  num = {1'b1, data[11:8]};
      3'b110:  num = {1'b0, data[7:4]};
      3'b111:  num = {1'b0, data[3:0]};
      default: num = 4'dx;
    endcase
  end

  always @(*) begin
    case (num)
      5'h0: seg = 8'b00111111;  //"0"
      5'h1: seg = 8'b00000110;  //"1"
      5'h2: seg = 8'b01011011;  //"2"
      5'h3: seg = 8'b01001111;  //"3"
      5'h4: seg = 8'b01100110;  //"4"
      5'h5: seg = 8'b01101101;  //"5"
      5'h6: seg = 8'b01111101;  //"6"
      5'h7: seg = 8'b00000111;  //"7"
      5'h8: seg = 8'b01111111;  //"8"
      5'h9: seg = 8'b01101111;  //"9"
      5'hA: seg = 8'b01110111;  //"A"
      5'hB: seg = 8'b01111100;  //"b"
      5'hC: seg = 8'b00111001;  //"c"
      5'hD: seg = 8'b01011110;  //"d"
      5'hE: seg = 8'b01111001;  //"E"
      5'hF: seg = 8'b01110001;  //"F"
      default: seg = 8'b00000000;  //"dark"
    endcase
  end

endmodule
